Radiation tolerant back biased CMOS VLSI

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6583470
SERIAL NO

09487767

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A CMOS circuit formed in a semiconductor substrate having improved immunity to total ionizing dose radiation, improved immunity to radiation induced latch up, and improved immunity to a single event upset. The architecture of the present invention can be utilized with the n-well, p-well, or dual-well processes. For example, a preferred embodiment of the present invention is described relative to a p-well process wherein the p-well is formed in an n-type substrate. A network of NMOS transistors is formed in the p-well, and a network of PMOS transistors is formed in the n-type substrate. A contact is electrically coupled to the p-well region and is coupled to first means for independently controlling the voltage in the p-well region. Another contact is electrically coupled to the n-type substrate and is coupled to second means for independently controlling the voltage in the n-type substrate. By controlling the p-well voltage, the effective threshold voltages of the n-channel transistors both drawn and parasitic can be dynamically tuned. Likewise, by controlling the n-type substrate, the effective threshold voltages of the p-channel transistors both drawn and parasitic can also be dynamically tuned. Preferably, by optimizing the threshold voltages of the n-channel and p-channel transistors, the total ionizing dose radiation effect will be neutralized and lower supply voltages can be utilized for the circuit which would result in the circuit requiring less power.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
SCIENCE & TECHNOLOGY CORPORATION @ UNMALBUQUERQUE, NM80

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gambles, Jody W Albuquerque, NM 6 71
Hass, Kenneth J Albuquerque, NM 2 51
Maki, Gary K Albuquerque, NM 8 145

Cited Art Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
5204841 Virtual multi-port RAM 69 1992
 
IDAHO RESEARCH FOUNDATION, INC. (3)
4873688 High-speed real-time Reed-Solomon decoder 41 1987
5111429 Single event upset hardening CMOS memory circuit 56 1990
5418473 Single event upset immune logic family 25 1992
 
AMI SEMICONDUCTOR, INC. (1)
4541067 Combinational logic structure using PASS transistors 71 1982
 
OMNET ASSOCIATES A CA PARTNERSHIP (1)
4587627 Computational method and apparatus for finite field arithmetic 39 1982
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
5481555 System and method for error detection and reducing simultaneous switching noise 30 1994
 
MICRON TECHNOLOGY, INC. (1)
* 6005797 Latch-up prevention for memory cells 30 1998
 
AEROFLEX COLORADO SPRINGS INC. (1)
5870332 High reliability logic circuit for radiation environment 30 1996
 
SCIENCE & TECHNOLOGY CORPORATION @ UNM (2)
5406513 Mechanism for preventing radiation induced latch-up in CMOS integrated circuits 54 1993
* 6232794 Electronic circuit with automatic signal conversion 11 1999
* Cited By Examiner

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (5)
* 7057180 Detector for alpha particle or cosmic ray 4 2003
* 2005/0012,045 DETECTOR FOR ALPHA PARTICLE OR COSMIC RAY 1 2003
7725870 Method for radiation tolerance by implant well notching 0 2007
* 7698681 Method for radiation tolerance by logic book folding 0 2007
* 2009/0045,840 Method for Radiation Tolerance by Logic Book Folding 2 2007
 
SONY CORPORATION (1)
* 7915657 Semiconductor integrated circuit 2 2009
 
INTEL CORPORATION (2)
* 7529118 Generalized interlocked register cell (GICE) 7 2007
* 2008/0239,793 Generalized Interlocked Register Cell (GICE) 1 2007
 
UNIVERSITY OF IDAHO (1)
* 7489538 Radiation tolerant combinational logic cell 5 2006
 
Defense Electronics Corporation (2)
* 9438025 Radiation hardened chip level integrated recovery apparatus, methods, and integrated circuits 0 2013
9720026 Radiation hardened chip level integrated recovery apparatus, methods, and integrated circuits 0 2016
 
GLOBALFOUNDRIES INC. (6)
7499308 Programmable heavy-ion sensing device for accelerated DRAM soft error detection 4 2007
7675789 Programmable heavy-ion sensing device for accelerated DRAM soft error detection 1 2008
7989282 Structure and method for latchup improvement using through wafer via latchup guard ring 3 2009
* 2010/0244,179 STRUCTURE AND METHOD FOR LATCHUP IMPROVEMENT USING THROUGH WAFER VIA LATCHUP GUARD RING 3 2009
8390074 Structure and method for latchup improvement using through wafer via latchup guard ring 0 2011
* 2011/0227,166 STRUCTURE AND METHOD FOR LATCHUP IMPROVEMENT USING THROUGH WAFER VIA LATCHUP GUARD RING 0 2011
 
The United States of America as represented by the Secretary of the Navy (1)
* 6777753 CMOS devices hardened against total dose radiation effects 5 2000
 
COBHAM DEFENSE ELECTRONIC SYSTEMS CORPORATION (3)
* 2007/0138,515 Dual field plate MESFET 3 2005
* 7485514 Method for fabricating a MESFET 0 2006
* 2007/0155,072 Method for fabricating a MESFET 1 2006
 
ICS, LLC (1)
8081010 Self restoring logic 5 2010
 
GOOGLE INC. (1)
7283410 Real-time adaptive SRAM array for high SEU immunity 38 2006
 
XILINX, INC. (1)
* 8981491 Memory array having improved radiation immunity 0 2012
 
NXP USA, INC. (3)
* 7892907 CMOS latch-up immunity 1 2008
8963256 CMOS device structures 0 2011
* 2011/0101,465 CMOS DEVICE STRUCTURES 3 2011
* Cited By Examiner