Semiconductor device and its manufacturing method
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United States of America Patent
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Jun 24, 2003
Grant Date -
May 2, 2002
app pub date -
Jul 19, 2001
filing date -
Jul 26, 2000
priority date (Note) -
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Abstract
In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is mounted on insulated substrate 12. Multiple stud bumps are stacked on top of the pads 20a which are located on the inner rows, and these stud bumps comprise stud bump stack 28. Conductive wire 22 connects the lands 18 on the insulated substrate with the corresponding bonding pads 20. The wire is formed with its beginning at the land and its end at the bonding pad. Via the stud bump stacks 28, the ends of conductive wire 22a on the inner pads are in a higher position than the ends of conductive wires 22b on the outer pads, so that the problem of neighboring conductive wires coming into contact does not occur.
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- 15 United States
- 10 France
- 8 Japan
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- 5 Korea
- 2 Other
Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| TEXAS INSTRUMENTS INCORPORATED | 12500 TI BLVD MS 3999 DALLAS TX 75243 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Karashima, Akira | Oita, JP | 8 | 156 |
| Masumoto, Kenji | Hiji, JP | 31 | 597 |
| Masumoto, Mutsumi | Beppu, JP | 56 | 674 |
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| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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