US Patent No: 6,583,503

Number of patents in Portfolio can not be more than 2000

Semiconductor package with stacked substrates and multiple semiconductor dice

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Importance

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Abstract

A semiconductor package comprising multiple stacked substrates having flip chips attached to the substrates with chip-on-board assembly techniques to achieve dense packaging. The substrates are preferably stacked atop one another by electric connections which are column-like structures. The electric connections achieve electric communication between the stacked substrates, must be of sufficient height to give clearance for the components mounted on the substrates, and should preferably be sufficiently strong enough to give support between the stacked substrates.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
MICRON TECHNOLOGY, INC.BOISE, ID18599

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Akram, Salman Boise, ID 829 21047
Brooks, Jerry M Caldwell, ID 194 4390

Cited Art

Patent Info (Count) # Cites Year
 
MICRON TECHNOLOGY, INC. (8)
5,109,320 System for connecting integrated circuit dies to a printed wiring board 47 1990
5,128,831 High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias 359 1991
5,300,801 Stacked capacitor construction 48 1993
5,496,775 Semiconductor device having ball-bonded pads 81 1994
5,494,841 Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells 87 1994
6,051,878 Method of constructing stacked packages 179 1999
6,222,265 Method of constructing stacked packages 108 1999
6,404,044 Semiconductor package with stacked substrates and multiple semiconductor dice 29 2001
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (5)
5,252,857 Stacked DCA memory chips 226 1991
5,473,814 Process for surface mounting flip chip carrier modules 58 1994
5,728,606 Electronic Package 22 1996
5,715,144 Multi-layer, multi-chip pyramid and circuit board structure 60 1996
5,729,440 Solder hierarchy for chip attachment to substrates 60 1997
 
FREESCALE SEMICONDUCTOR, INC. (4)
5,222,014 Three-dimensional multi-chip pad array carrier 390 1992
5,239,198 Overmolded semiconductor device having solder ball and edge lead connective structure 305 1992
5,612,576 Self-opening vent hole in an overmolded semiconductor device 84 1992
5,535,101 Leadless integrated circuit package 197 1992
 
NATIONAL SEMICONDUCTOR CORPORATION (3)
5,422,435 Stacked multi-chip modules and method of manufacturing 284 1992
5,512,765 Extendable circuit architecture 56 1994
5,495,398 Stacked multi-chip modules and method of manufacturing 216 1995
 
HUGHES AIRCRAFT COMPANY (2)
5,481,134 Stacked high density interconnected integrated circuit system 23 1994
5,498,905 Layered features for co-fired module integration 9 1994
 
ROUND ROCK RESEARCH, LLC (2)
5,291,061 Multi-chip stacked devices 196 1993
5,323,060 Multichip module having a stacked chip arrangement 313 1993
 
SAMSUNG ELECTRONICS CO., LTD. (2)
5,099,306 Stacked tab leadframe assembly 31 1991
5,594,275 J-leaded semiconductor package having a plurality of stacked ball grid array packages 135 1994
 
FUJITSU SEMICONDUCTOR LIMITED (1)
5,508,565 Semiconductor device having a plurality of chips having identical circuit arrangement sealed in package 121 1994
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
4,954,878 Method of packaging and powering integrated circuit chips and the chip assembly formed thereby 138 1989
 
INTEL CORPORATION (1)
5,506,756 Tape BGA package die-up/die down 77 1995
 
INTERCONNECT SYSTEMS, INC. (1)
5,513,076 Multi-level assemblies for interconnecting integrated circuits 27 1995
 
LSI LOGIC CORPORATION (1)
5,639,696 Microelectronic integrated circuit mounted on circuit board with solder column grid array interconnection, and method of fabricating the solder column grid array 60 1996
 
NEC CORPORATION (1)
5,705,858 Packaging structure for a hermetically sealed flip chip semiconductor device 53 1994
 
SEIKO EPSON CORPORATION (1)
5,498,902 Semiconductor device and its manufacturing method 37 1994
 
SILICON VALLEY BANK (1)
5,477,082 Bi-planar multi-chip module 217 1994
 
STOVOKOR TECHNOLOGY LLC (1)
5,403,784 Process for manufacturing a stacked multiple leadframe semiconductor package using an alignment template 45 1993
 
SUN MICROSYSTEMS, INC. (1)
5,512,780 Inorganic chip-to-package interconnection circuit 6 1994
 
UNITED MICROELECTRONICS CORP. (1)
5,466,627 Stacked capacitor process using BPSG precipitates 16 1994
 
WHITE MICROELECTRONICS DIV. OF BOWMAR INSTRUMENT CORP. (1)
5,434,745 Stacked silicon die carrier assembly 173 1994

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
AMKOR TECHNOLOGY, INC. (91)
7,071,541 Plastic integrated circuit package and method and leadframe for making the package 1 2003
6,965,157 Semiconductor package with exposed die pad and body-locking leadframe 9 2003
7,115,445 Semiconductor package having reduced thickness 1 2004
7,057,268 Cavity case with clip/plug for use on multi-media card 3 2004
7,091,594 Leadframe type semiconductor package having reduced inductance and its manufacturing method 7 2004
7,170,150 Lead frame for semiconductor package 2 2004
6,844,615 Leadframe package for semiconductor devices 7 2004
7,005,326 Method of making an integrated circuit package 5 2004
7,190,062 Embedded leadframe semiconductor package 24 2004
7,067,908 Semiconductor package having improved adhesiveness and ground bonding 4 2004
7,211,471 Exposed lead QFP package fabricated through the use of a partial saw process 42 2004
7,598,598 Offset etched corner leads for semiconductor package 0 2004
7,202,554 Semiconductor package and its manufacturing method 14 2004
7,045,882 Semiconductor package including flip chip 7 2004
6,953,988 Semiconductor package 18 2004
7,217,991 Fan-in leadframe semiconductor package 7 2004
7,253,503 Integrated circuit device packages and substrates for making the packages 41 2004
7,001,799 Method of making a leadframe for semiconductor devices 2 2004
7,064,009 Thermally enhanced chip scale lead on chip semiconductor package and method of making same 7 2004
7,030,474 Plastic integrated circuit package and method and leadframe for making the package 2 2004
7,176,062 Lead-frame method and assembly for interconnecting circuits within a circuit module 0 2005
7,214,326 Increased capacity leadframe and semiconductor package using the same 4 2005
7,247,523 Two-sided wafer escape package 15 2005
6,995,459 Semiconductor package with increased number of input and output pins 49 2005
7,192,807 Wafer level package and fabrication method 17 2005
7,045,883 Thermally enhanced chip scale lead on chip semiconductor package and method of making same 5 2005
7,507,603 Etch singulated semiconductor package 8 2005
7,361,533 Stacked embedded leadframe 20 2005
7,572,681 Embedded electronic component package 19 2005
7,112,474 Method of making an integrated circuit package 1 2005
7,564,122 Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant 1 2006
8,410,585 Leadframe and semiconductor package made using the leadframe 0 2006
7,535,085 Semiconductor package having improved adhesiveness and ground bonding 2 2006
7,902,660 Substrate for semiconductor device and manufacturing method thereof 15 2006
7,968,998 Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package 2 2006
7,321,162 Semiconductor package having reduced thickness 0 2006
7,332,375 Method of making an integrated circuit package 0 2006
7,521,294 Lead frame for semiconductor package 5 2006
7,714,431 Electronic component package comprising fan-out and fan-in traces 20 2006
7,687,893 Semiconductor package having leadframe with exposed anchor pads 3 2006
7,829,990 Stackable semiconductor package including laminate interposer 1 2007
7,982,297 Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same 1 2007
7,420,272 Two-sided wafer escape package 16 2007
7,723,210 Direct-write wafer level chip scale package 6 2007
7,977,774 Fusion quad flat semiconductor package 3 2007
7,687,899 Dual laminate package structure with embedded elements 5 2007
7,777,351 Thin stacked interposer package 23 2007
8,089,159 Semiconductor package with increased I/O density and method of making the same 0 2007
7,847,386 Reduced size stacked semiconductor package and method of making the same 0 2007
7,560,804 Integrated circuit package and method of making the same 1 2008
7,956,453 Semiconductor package with patterning layer and method of making same 0 2008
7,723,852 Stacked semiconductor package and method of making same 4 2008
8,067,821 Flat semiconductor package with half package molding 2 2008
7,768,135 Semiconductor package with fast power-up cycle and method of making same 3 2008
7,808,084 Semiconductor package with half-etched locking features 1 2008
8,125,064 Increased I/O semiconductor package and method of making same 0 2008
8,184,453 Increased capacity semiconductor package 1 2008
7,692,286 Two-sided fan-out wafer escape package 20 2008
7,847,392 Semiconductor device including leadframe with increased I/O 5 2008
7,989,933 Increased I/O leadframe and semiconductor device including same 1 2008
8,008,758 Semiconductor device with increased I/O leadframe 3 2008
8,089,145 Semiconductor device including increased capacity leadframe 1 2008
8,072,050 Semiconductor device with increased I/O leadframe including passive device 0 2008
7,875,963 Semiconductor device including leadframe having power bars and increased I/O 3 2008
7,982,298 Package in package semiconductor device 1 2008
8,058,715 Package in package device for RF transceiver module 1 2009
7,732,899 Etch singulated semiconductor package 0 2009
8,026,589 Reduced profile stackable semiconductor package 4 2009
7,960,818 Conformal shield on punch QFN semiconductor package 0 2009
7,928,542 Lead frame for semiconductor package 1 2009
7,977,163 Embedded electronic component package fabrication method 2 2009
8,089,141 Semiconductor package having leadframe with exposed anchor pads 0 2010
7,872,343 Dual laminate package structure with embedded elements 1 2010
8,188,584 Direct-write wafer level chip scale package 0 2010
7,932,595 Electronic component package comprising fan-out traces 4 2010
8,324,511 Through via nub reveal method and structure 0 2010
7,906,855 Stacked semiconductor package and method of making same 1 2010
8,294,276 Semiconductor device and fabricating method thereof 0 2010
8,084,868 Semiconductor package with fast power-up cycle and method of making same 0 2010
8,319,338 Thin stacked interposer package 0 2010
8,299,602 Semiconductor device including leadframe with increased I/O 0 2010
8,283,767 Dual laminate package structure with embedded elements 0 2010
8,188,579 Semiconductor device including leadframe having power bars and increased I/O 1 2010
8,390,130 Through via recessed reveal structure and method 0 2011
8,318,287 Integrated circuit package and method of making the same 0 2011
8,102,037 Leadframe for semiconductor package 0 2011
8,119,455 Wafer level package fabrication method 1 2011
8,304,866 Fusion quad flat semiconductor package 0 2011
8,432,023 Increased I/O leadframe and semiconductor device including same 0 2011
8,227,921 Semiconductor package with increased I/O density and method of making same 0 2011
8,298,866 Wafer level package and fabrication method 0 2012
 
STATS CHIPPAC LTD. (19)
7,253,511 Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package 28 2004
7,622,325 Integrated circuit package system including high-density small footprint system-in-package 5 2005
7,768,125 Multi-chip package system 4 2006
7,750,482 Integrated circuit package system including zero fillet resin 0 2006
8,026,129 Stacked integrated circuits package system with passive components 0 2006
7,429,786 Semiconductor package including second substrate and having exposed substrate surfaces on upper and lower sides 38 2006
7,429,787 Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides 22 2006
7,372,141 Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides 33 2006
7,582,960 Multiple chip package module including die stacked over encapsulated package 1 2006
7,394,148 Module having stacked chip scale semiconductor packages 14 2006
7,692,279 Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package 2 2007
7,687,313 Method of fabricating a semiconductor multi package module having an inverted package stacked over ball grid array (BGA) package 5 2008
7,687,315 Stacked integrated circuit package system and method of manufacture therefor 2 2008
7,855,100 Integrated circuit package system with an encapsulant cavity and method of fabrication thereof 3 2008
7,645,634 Method of fabricating module having stacked chip scale semiconductor packages 1 2008
7,652,376 Integrated circuit package system including stacked die 4 2008
7,829,382 Method for making semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package 0 2010
8,021,924 Encapsulant cavity integrated circuit package system and method of fabrication thereof 2 2010
8,309,397 Integrated circuit packaging system with a component in an encapsulant cavity and method of fabrication thereof 0 2011
 
CHIPPAC, INC. (9)
7,682,873 Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages 0 2006
7,279,361 Method for making a semiconductor multi-package module having wire bond interconnect between stacked packages 5 2006
8,030,134 Stacked semiconductor package having adhesive/spacer structure and insulation 1 2006
7,351,610 Method of fabricating a semiconductor multi-package module having a second package substrate with an exposed metal layer wire bonded to a first package substrate 3 2007
7,364,946 Method of fabricating a semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package 8 2007
7,358,115 Method of fabricating a semiconductor assembly including chip scale package and second substrate with exposed substrate surfaces on upper and lower sides 3 2007
8,143,100 Method of fabricating a semiconductor multi-package module having wire bond interconnect between stacked packages 0 2007
7,749,807 Method of fabricating a semiconductor multipackage module including a processor and memory package assemblies 0 2007
7,935,572 Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages 1 2010
 
MICRON TECHNOLOGY, INC. (8)
7,115,998 Multi-component integrated circuit contacts 9 2002
6,979,895 Semiconductor assembly of stacked substrates and multiple semiconductor dice 15 2003
7,446,028 Multi-component integrated circuit contacts 3 2005
7,663,232 Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems 3 2006
7,719,120 Multi-component integrated circuit contacts 1 2006
8,106,491 Methods of forming stacked semiconductor devices with a leadframe and associated assemblies 2 2007
8,124,456 Methods for securing semiconductor devices using elongated fasteners 0 2010
8,268,715 Multi-component integrated circuit contacts 0 2010
 
SANDISK TECHNOLOGIES INC. (5)
7,615,409 Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages 4 2006
7,550,834 Stacked, interconnected semiconductor packages 6 2006
8,053,880 Stacked, interconnected semiconductor package 0 2009
8,110,439 Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages 0 2009
8,053,276 Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages 2 2009
 
INTEGRATED MEMORY TECHNOLOGIES, INC. (3)
7,009,244 Scalable flash EEPROM memory cell with notched floating gate and graded source region 4 2004
7,407,857 Method of making a scalable flash EEPROM memory cell with notched floating gate and graded source region 2 2006
7,199,424 Scalable flash EEPROM memory cell with notched floating gate and graded source region 0 2006
 
SANMINA-SCI CORPORATION (2)
7,180,165 Stackable electronic assembly 26 2003
RE42363 Stackable electronic assembly 3 2010
 
SEIKO EPSON CORPORATION (2)
7,087,989 Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device 6 2004
7,436,061 Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device 1 2006
 
APPLE INC. (1)
7,729,131 Multiple circuit board arrangements in electronic devices 2 2007
 
BRIDGE SEMICONDUCTOR CORPORATION (1)
6,744,126 Multichip semiconductor package device 14 2002
 
ELPIDA MEMORY, INC. (1)
7,573,128 Semiconductor module in which a semiconductor package is bonded on a mount substrate 0 2004
 
FAIRCHILD SEMICONDUCTOR CORPORATION (1)
7,952,204 Semiconductor die packages with multiple integrated substrates, systems using the same, and methods using the same 0 2008
 
INTEL CORPORATION (1)
7,235,870 Microelectronic multi-chip module 7 2004
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
6,900,545 Variable thickness pads on a substrate surface 24 2000
 
KINGSTON TECHNOLOGY CORPORATION (1)
6,686,656 Integrated multi-chip chip scale package 31 2003
 
QIMONDA AG (1)
6,714,418 Method for producing an electronic component having a plurality of chips that are stacked one above the other and contact-connected to one another 40 2002
 
SILICONWARE PRECISION INDUSTRIES CO., LTD. (1)
6,828,665 Module device of stacked semiconductor packages and method for fabricating the same 77 2002
 
OTHER [CHECK PATENT PROFILE FOR ASSIGNMENT INFORMATION] (3)
8,440,554 Through via connected backside embedded circuit features structure and method 0 2010
8,441,110 Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package 0 2011
8,445,997 Stacked packaged integrated circuit devices 0 2012

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