Read compression in a memory
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United States of America Patent
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Jun 24, 2003
Grant Date -
Apr 18, 2002
app pub date -
Sep 21, 2001
filing date -
Aug 30, 2000
priority date (Note) -
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Abstract
A memory device has multiple selectable read data paths. Some of the read data paths include compression circuitry to compress data and decrease test time by testing multiple memories in parallel and/or multiple array banks from the same memory in parallel. A non-compression read path is provided to by-pass the compression circuitry. During memory read operations, therefore, data can be coupled to output buffers without being subjected to delays through a compression circuit. A first compression path can be selected to couple 16 bits from 1 memory array bank to 4 output connections. A second compression path can be selected to couple 64 bits from 4 memory array banks to 4 output connections.
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