Importance

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Abstract

A circuit arrangement, apparatus and method control the transfer of data into an intermediate buffer associated with a split transaction bus by conditioning such transfer on both the amount of free space in the intermediate buffer and whether a data transfer request associated with such transfer of data is ready to be processed at a shared resource that is the target for the data transfer request. In an example embodiment, data transfer requests represent AGP write transactions to a shared memory, and control logic for an intermediate buffer used to store the write data associated with such transactions is configured to selectively inhibit the storage of write data associated with an AGP write transaction unless both at least one block of free space (representing the minimum amount of space necessary to start the write transaction) exists in the intermediate buffer, and the shared memory is ready to process the transaction.

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First Claim