Variable rotational assignment of interconnect levels in integrated circuit fabrication
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United States of America Patent
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Jul 1, 2003
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N/A
app pub date -
Oct 31, 2000
filing date -
Oct 31, 2000
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Abstract
Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.
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