Memory device having wide margin of data reading operation, for storing data by change in electric resistance value
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 1, 2003
Grant Date -
N/A
app pub date -
Sep 4, 2001
filing date -
Mar 5, 2001
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Read word lines are disposed in correspondence with rows of memory cells arranged in a matrix, and bit lines and reference voltage lines are disposed in correspondence with the columns. A data read current is passed through a current path passing a selected memory cell, which is formed between a data read circuit and a read reference voltage via a data bus, a column selection gate, a bit line, and a reference voltage line. The data read circuit detects a voltage change occurring in the selected memory cell due to the data read current and outputs read data. A sum of an electric resistance value of the bit line and an electric resistance value of the reference voltage line in a portion included in the current path is set to be almost constant without depending on a row to which the selected memory cell belongs.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully