Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 8, 2003
Grant Date -
Dec 26, 2002
app pub date -
Apr 23, 2001
filing date -
Oct 9, 1997
priority date (Note) -
In Force
status (Latency Note)
![]() |
A preliminary load of PAIR data current through [] has been loaded. Any more recent PAIR data will be loaded within twenty-four hours. |
PAIR data current through []
A preliminary load of cached data will be loaded soon.
Any more recent PAIR data will be loaded within twenty-four hours.
![]() |
Next PAIR Update Scheduled on [ ] |

Importance
|
US Family Size
|
Non-US Coverage
|
|
Patent Longevity
|
Forward Citations
|
Abstract
A Variable Grain Architecture (VGA) is used for synthesizing from primitive building elements (CBE's) an appropriate amount of dynamic multiplexing capability for each given task. Unused ones of such Configurable Building Elements (CBE's) are reconfigured to carry out further logic functions in place of the dynamic multiplexing functions. Each CBE may be programmably configured to provide no more than a 2-to-1 dynamic multiplexer (2:1 DyMUX). The dynamically-selectable output of such a synthesized 2:1 DyMUX may then be output onto a shared interconnect line. Pairs of CBE's may be synthetically combined to efficiently define 4:1 DyMUX's with each such 4:1 multiplexer occupying a Configurable Building Block (CBB) structure. Pairs of CBB's may be synthetically combined to efficiently define 8:1 DyMUX's with each such synthesized 8:1 multiplexer occupying a vertically or horizontally-extending leg portion of an L-shaped, VGB structure (Variable Grain Block). The so-configured leg portion of the VGB may then output the signal selected by its 8:1 DyMUX onto a shared interconnect line that is drivable by the VGB leg. Pairs or quartets of VGB's may be synthetically combined to efficiently define higher order, N:1 DyMUX's.
First Claim
Family
- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| LATTICE SEMICONDUCTOR CORPORATION | 5555 NE MOORE CT HILLSBORO OR 97124 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Agrawal, Om P | Los Altos, CA | 127 | 5023 |
| Chang, Herman M | Cupertino, CA | 24 | 1142 |
| Nguyen, Bai | San Jose, CA | 34 | 866 |
| Sharpe-Geisler, Bradley A | San Jose, CA | 97 | 2796 |
| Tran, Giap H | San Jose, CA | 19 | 782 |
Cited Art Landscape
- No Cited Art to Display

Patent Citation Ranking
Forward Cite Landscape
- No Forward Cites to Display

Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
Full Text
Legal Events
Matter Detail
Update Public Data
Dismiss
Edit
Save
Renewals Detail
Edit
Save
Note
The template below is formatted to ensure compatibility with our system.
Provide tags with | separated like (tags1|tags2).
Maximum length is 128 characters for Customer Application No
Mandatory Fields * - 'MatterType','AppType','Country','Title','SerialNo'.
Acceptable Date Format - 'MM/DD/YYYY'.
Acceptable Filing/App Types -
- Continuation/Divisional
- Original
- Paris Convention
- PCT National
- With Priority
- EP Validation
- Provisional Conversion
- Reissue
- Provisional
- Foreign Extension
Acceptable Status -
- Pending
- Abandoned
- Unfiled
- Expired
- Granted
Acceptable Matter Types -
- Patent
- Utility Model
- Supplemental Protection Certificate
- Design
- Inventor Certificate
- Plant
- Statutory Invention Reg
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Success
E-mail has been sent successfully.
Failure
Some error occured while sending email. Please check e-mail and try again!
PAIR load has been initiated
A preliminary load of cached data will be loaded soon. Current PAIR data will be loaded within twenty four hours.
File History PDF
Thank you for your purchase! The File Wrapper for Patent Number 6590415 will be available within the next 24 hours.
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully
Important Notes on Latency of Status data
Please note there is up to 60 days of latency in this Status indicator for certain status conditions. You can obtain up-to-date Status indicator readings by ordering PAIR for the file.
An application with the status "Published" (which means it is pending) may be recently abandoned, but not yet updated to reflect its abandoned status. However, an application filed less than one year ago is unlikely to be abandoned.
A patent with the status "Granted" may be recently expired, but not yet updated to reflect its expired status. However, it is highly unlikely a patent less than 3.5 years old would be expired.
An application with the status "Abandoned" is almost always current, but there is a small chance it was recently revived and the status not yet updated.
Important Note on Priority Date data
This priority date is an estimated earliest priority date and is purely an estimation. This date should not be taken as legal conclusion. No representations are made as to the accuracy of the date listed. Please consult a legal professional before relying on this date.
We are sorry but your current selection exceeds the maximum number of portfolios (0) for this membership level. Upgrade to our Level for up to -1 portfolios!.

