Apparatus and method for inputting address signals in semiconductor memory device
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United States of America Patent
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Jul 8, 2003
Grant Date -
Mar 20, 2003
app pub date -
Jan 15, 2002
filing date -
Sep 18, 2001
priority date (Note) -
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Abstract
Disclosed is an address input apparatus of a semiconductor memory device having a unit cell including a capacitor, comprising an internal clock generator for generating and outputting an internal clock signal at a fixed period and a buffering and sampling unit for buffering an inputted address and sampling the address in the fixed period in response to the internal clock signal.
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