Mechanism to reorder memory read and write transactions for reduced latency and increased bandwidth
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United States of America Patent
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Jul 8, 2003
Grant Date -
N/A
app pub date -
Aug 31, 2000
filing date -
Aug 31, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A system and method is disclosed to increase computer memory system performance by reducing lost clock cycles caused by bus turnarounds. The computer system contains one or more processors each including a memory controller containing a page table, the page table organized into a plurality of rows with each row able to store an address of an open memory page. The memory controller also contains a precharge queue, a Row-address-select ('RAS') queue, a Column-address-select ('CAS') Read queue, and a CAS Write queue. The CAS Read queue and CAS Write queue outputs are connected to a 2-to-1 multiplexer. The 2-to-1 multiplexer streams groups of read requests and groups of write requests to main memory resulting in fewer lost clock cycles caused by bus turnarounds. The memory controller places system memory read requests into the CAS Read queue and system memory write requests into the CAS Write queue.
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