Importance

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Abstract

There is provided a semiconductor device, such as a TFT, with a vertical drain offset region. The device contains a substrate having an upper first surface, a semiconductor channel region of a first conductivity type over the first surface, a gate electrode and a gate insulating layer between the gate electrode and the channel region. The device also contains a heavily doped semiconductor source region of a second conductivity type, a heavily doped semiconductor drain region of a second conductivity type. An intrinsic or lightly doped semiconductor drain offset region is located between the drain region and the channel region, such that the drain region is offset from the channel region at least partially in a direction perpendicular to the first surface.

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First Claim