Importance

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Abstract

An improved memory device employs a DRAM array for data storage. In the device, a special row address decoder simultaneously asserts a corresponding unique pair of the wordlines in response to each received valid row address, so that a single valid row address simultaneously accesses two rows of memory cells in the array. The device differentially writes and reads each bit of data across a pair of memory cells; each one of the pair of memory cells being within a different respective row of the array, and the two different rows together corresponding to one of the unique pairs of wordlines asserted by the row address decoder responsive to a valid row address. This arrangement obviates the need for high voltage boosting circuits and thereby reduces power consumption.

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First Claim