Importance

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Abstract

A circuit is provided that includes a bridge circuit for connecting a first bus to a second bus. The bridge circuit also includes a first bus interface coupled to the first bus and is adapted to receive a plurality of transactions from the first bus. Each transaction has an address targeting the second bus and data the length of which defines a transaction size. A request data engine for issuing requests on a second bus is also provided. The request data engine is capable of assigning a unique encoded header to data streams. Control logic is provided that is adapted to store a first portion of a first transaction of the plurality of transactions in a memory coupled between the first bus and the second bus. Management logic is provided that is adapted to manage multiple out-of-order data streams wherein the data streams may remain outstanding to the bridge circuit. Additionally, a method is provided that includes capturing a data stream request header. Determining which data stream a request is mapped into. Assigning a unique encoded header to a data packet. Issuing request packets with the unique encoded header. Receiving completion request data packets. Setting a first pointer in a memory. Incrementing a portion of a memory address. Checking if all data packets are stored in the memory. And, managing multiple out-of-order data streams wherein the data streams may remain outstanding to a bridge circuit.

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First Claim