Cache memory with dual-way arrays and multiplexed parallel output
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United States of America Patent
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Jul 15, 2003
Issued Date -
N/A
app pub date -
Mar 7, 1997
filing date -
Oct 14, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A two-way cache memory having multiplexed outputs and alternating ways is disclosed. Multiplexed outputs enable the cache memory to be more densely packed and implemented with fewer sense amplifiers. Alternating ways enable two distinct cache access patterns. According to a first access pattern, two doublewords in the same way may be accessed simultaneously. Such access facilities the leading of data into main memory. According to a second access pattern, two doublewords in the same location but in different ways may be accessed simultaneously. Such access facilitates the loading a particular word into a register file.
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