DRAM core refresh with reduced spike current
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United States of America Patent
Stats
-
Jul 22, 2003
Grant Date -
Jun 13, 2002
app pub date -
Jan 29, 2002
filing date -
Oct 10, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge currents during a refresh operation, as compared to normal memory access. Unlike normal memory accesses, data is not needed, and a fast access time is not required. This allows the current to be spread using different circuitry for driving the current to lessen current spikes. The spread current is still maintained within the timing of a normal memory access.
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