Semiconductor device with reduced current consumption in standby state

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United States of America Patent

PATENT NO 6597617
SERIAL NO

10167437

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Abstract

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A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

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Patent Owner(s)

Patent OwnerAddress
RENESAS ELECTRONICS CORPORATIONTOKYO 135-0061

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hidaka, Hideto Hyogo, JP 318 6568
Ishikawa, Masatoshi Hyogo, JP 104 1706
Kato, Hiroshi Hyogo, JP 503 7120
Ooishi, Tsukasa Hyogo, JP 317 7821
Tsuji, Takaharu Hyogo, JP 40 1182

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