Common scalable queuing and dequeuing architecture and method relative to network switch data rate
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United States of America Patent
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Jul 22, 2003
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app pub date -
May 21, 1999
filing date -
May 21, 1999
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Abstract
A network switch arrangement and method for providing a common architecture for queuing and dequeuing of data frames as they are transferred from a switch port to an external memory and similarly retrieved from the external memory to the switch port, irrespective of the particular data rate of the port. Logic controlling the actual data path is partitioned from logic responding to port data rate information by providing a 'handshaking' communication arrangement between the two logics independent of the data rate. Hence, scalability of the data path over a wide range of data rates may be achieved while maintaining a single, common logic architecture.
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