Data transfer with highly granular cacheability control between memory and a scratchpad area
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 22, 2003
Issued Date -
N/A
app pub date -
Oct 22, 1997
filing date -
Oct 6, 1995
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A processing system having a CPU core and a cache transfers data between a first block of memory and a second block of memory that is preferably partitioned out of the cache as a non-cacheable scratchpad area and performs address calculations with protection and privilege checks without polluting the cache. Responsive to executing a predetermined instruction, the CPU core signals the cache to prevent caching data during transfer from system to scratchpad memory thereby reducing the number of bus turnarounds while maintaining byte granularity addressability.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully