Processor and method that accelerate evaluation of pairs of condition-setting and branch instructions
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United States of America Patent
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Jul 22, 2003
Grant Date -
N/A
app pub date -
Dec 10, 1999
filing date -
Dec 10, 1999
priority date (Note) -
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Abstract
A processor that promotes accelerated resolution of conditional branch instructions includes an instruction sequencer that fetches a plurality of instructions and a detector that detects, among the plurality of fetched instructions, a condition-setting instruction and a conditional branch instruction that depends upon the condition-setting instruction. The processor further includes a decoder that decodes the conditional branch instruction to produce a decoded condition type and an execution unit. In response to the detection of the condition-setting instruction and the conditional branch instruction, the execution unit resolves the conditional branch instruction by evaluating the condition-setting instruction and the decoded condition type in a single operation. Because the condition code bits are not computed or stored as an intermediate result as in prior art processors, branch resolution is accelerated.
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