Precoding branch instructions to reduce branch-penalty in pipelined processors
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United States of America Patent
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Jul 22, 2003
Grant Date -
N/A
app pub date -
Dec 29, 1998
filing date -
Dec 29, 1998
priority date (Note) -
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Abstract
A method of reducing the branch penalty in a microprocessor includes predecoding the instruction to determine whether an instruction is a branch, the length of the instruction, and prediction marker information for the instruction should it be a branch. The target of the branch is relayed to the align stage of the microprocessor to readjust the read pointer to point to the target of the branch if the instruction is a branch. An apparatus for reducing the branch penalty in a microprocessor includes a branch predecode and taken resolution unit which determines whether an instruction is a predicted taken branch, and relays that information to the align stage of the microprocessor to deliver the target of the branch to the align stage as early as possible.
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