US Patent No: 6,599,764

Number of patents in Portfolio can not be more than 2000

Isolation testing scheme for multi-die packages

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Abstract

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A test platform is configured to test a mult-die package having at a first die and a second die. The test platform includes a first lead that is connected to the VCC input on the first die. The test platform also includes a second lead that is connected to VCCIO input on the second die. The VCC input on the second die is connected to ground. The I/O pin of the second die can then be tri-stated using a control circuit disposed between the pre-driver and the driver of the I/O buffer.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
ALTERA CORPORATIONSAN JOSE, CA3724

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ang, Boon Jin Penang, MY 29 151
Cheung, Sammy Pleasanton, CA 11 107
Chua, Kar Keng Penang, MY 30 77

Cited Art Landscape

Patent Info (Count) # Cites Year
 
ATI TECHNOLOGIES ULC (1)
* 6,351,681 Method and apparatus for a multi-chip module that is testable and reconfigurable based on testing results 32 1998
 
MICRON TECHNOLOGY, INC. (2)
* 5,796,746 Device and method for testing integrated circuit dice in an integrated circuit module 47 1996
* 6,240,535 Device and method for testing integrated circuit dice in an integrated circuit module 22 1998
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
FREESCALE SEMICONDUCTOR, INC. (1)
7,262,615 Method and apparatus for testing a semiconductor structure having top-side and bottom-side connections 13 2005
 
MICRON TECHNOLOGY, INC. (1)
7,755,204 Stacked die module including multiple adhesives that cure at different temperatures 1 2003
 
SANDISK TECHNOLOGIES INC. (3)
* 6,797,538 Memory package 8 2003
7,064,003 Memory package 4 2004
7,429,781 Memory package 3 2006
 
INFINEON TECHNOLOGIES AG (1)
* 7,855,463 Method for producing a circuit module comprising at least one integrated circuit 3 2007
* Cited By Examiner