Technique for underfilling stacked chips on a cavity MLC module
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United States of America Patent
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Jul 29, 2003
Issued Date -
N/A
app pub date -
Apr 23, 2001
filing date -
Jun 29, 1999
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An electronic device is provided comprising a stacked integrated circuit chip assembly wherein the top chip of the assembly is solder connected to the surface of an interconnection substrate with the other chips of the assembly being enclosed in a cavity in the interconnection substrate wherein the cavity and electrical connections of the assembly and between the substrate and top chip are sealed by supplying an encapsulant to the cavity through a through opening in the substrate which communicates with the cavity.
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