Chip-core framework for systems-on-a-chip
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United States of America Patent
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Jul 29, 2003
Grant Date -
N/A
app pub date -
May 2, 2000
filing date -
Jan 20, 2000
priority date (Note) -
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Abstract
A system-on-chip interconnection structure and method uses unidirectional buses only, central shared memory controllers, separate interconnects for high-speed and low-speed peripherals, zero wait-state register accesses, application-specific memory map and peripherals, application-specific test methodology, allowances for cache controllers, and good fits with standard ASIC flow and tools.
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