Count/address generation circuitry
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United States of America Patent
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Jul 29, 2003
Issued Date -
N/A
app pub date -
Dec 30, 1999
filing date -
Dec 30, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
According to one embodiment of the invention, an apparatus that includes a first and second counter both including a count computation circuit and an upper bound circuit. The output of the upper bound circuit of the first counter is coupled to the count computation circuit and upper bound circuit of the second counter. The apparatus also includes a lookup table addressed by the current count value of the first counter, as well as a combining circuit coupled to the output of the lookup table and to receive the current count value of the second counter.
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