Method for making large-scale ASIC using pre-engineered long distance routing structure
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 29, 2003
Grant Date -
N/A
app pub date -
Jun 27, 2001
filing date -
Jun 27, 2001
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Optimal routing line segments and associated buffers are pre-engineered for each family of ASIC chips by simulating wires segments of various lengths using distributed resistance and capacitance wire models, and by estimating crosstalk from neighboring line segments. During ASIC design, space is reserved on the ASIC substrate for fabricating the buffers, which are selectively connected by local metal and diffusion structures to form long distance interconnections. Signals are passed from an ASIC circuit structure to a selected long distance interconnection by connecting an output terminal of the ASIC structure either to the input terminal of a buffer located at one end of the interconnection, or by connecting the output terminal directed to a line segment of the interconnection.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully