Semiconductor memory apparatus having cell blocks and column drivers with a column address decoding module and a column drive enable signal generation module arranged to effectively reduce chip size
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United States of America Patent
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Aug 5, 2003
Grant Date -
Oct 24, 2002
app pub date -
Mar 29, 2002
filing date -
Apr 5, 2001
priority date (Note) -
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Abstract
A semiconductor memory device including a first memory cell block and a second memory cell block, both cell blocks having memory cells arranged in a matrix, and a common preamplifier/write driver located between and shared by the first memory cell block and the second memory cell block. The first memory cell block and the second memory cell block are aligned in a direction parallel to columns of the memory cells.
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