Reading a FIFO in dual clock domains

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6604179
APP PUB NO 20020129196A1
SERIAL NO

09532428

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Abstract

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A first-in first-out buffer (FIFO) with multiple outputs. The FIFO has an input for writing data into the FIFO. The FIFO has multiple outputs for reading the data out of the FIFO. Each output is independent from the other outputs, and can be used to read data from a different address at a different time using a different clock signal. In one embodiment, the FIFO is implemented as a storage array with circular pointers to repeatedly loop through the addressable locations. It includes a write pointer to indicate which address represents the input. It includes multiple read pointers to indicate which addresses represent the outputs. Overrun prevention logic is used to assure that the write pointer will not cause new data to be written into any address that has not been read by all outputs, and to assure that data will not be read from any address that has not been written into.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BLVD SANTA CLARA CA 95054

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Volk, Andrew M Granite Bay, CA 63 2204
Williams, Michael W Citrus Heights, CA 50 1743

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