Master/slave processor memory inter accessability in an integrated embedded system
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United States of America Patent
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Aug 5, 2003
Grant Date -
N/A
app pub date -
May 22, 2000
filing date -
May 22, 2000
priority date (Note) -
Expired
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Abstract
An apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) sections. The one or more second processors may each comprise a read only memory (ROM) section and a second RAM section. The one or more first processors may be configured to operate in either (i) a first mode that executes code stored in the one or more ROM sections or (ii) a second mode that processes code stored in the one or more first RAM sections. The one or more second processors may be configured to execute code from either (i) the one or more ROM sections or (ii) the one or more second RAM sections. The apparatus may provide interoperability that may increase system observability and decrease system debugging complexity.
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