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Abstract

A scalable stacked-gate flash memory device and its high-density memory arrays are disclosed by this invention. There are four different spacer techniques used to fabricate a scalable stacked-gate flash memory device: the first spacer technique is used to form the buffer-oxide spacers for implanting the channel stops of shallow-trench-isolation and oxidizing the etched surface of shallow trenches without sacrificing the active width of non-volatile semiconductor memory devices; the second spacer technique is used to highly adjust the coupling ratio of the self-aligned floating gate using a shallow-trench-isolation (STI) structure so that the applied control-gate voltage for programming and erase can be reduced; the third spacer technique is used to define the gate length of a scalable stacked-gate structure; and the fourth spacer technique is used to form the sidewall spacers for self-aligned source/drain implant, self-aligned source/drain or common buried-source silicidation, and self-aligned contacts. The scalable in here means the gate length of a stacked-gate flash memory device can be adjustable to be much smaller than the minimum feature size of technology used and high-density stacked-gate flash memory device arrays using NOR and NAND architectures are obtained. As a consequence, the scalable stacked-gate flash memory device of the present invention can be used to implement high-density, high-speed, low voltage and low-power flash memory array and system for mass storage applications.

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First Claim