Cross-correlation timing calibration for wafer-level IC tester interconnect systems
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United States of America Patent
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Aug 12, 2003
Grant Date -
Apr 25, 2002
app pub date -
Dec 29, 2000
filing date -
Jun 20, 2000
priority date (Note) -
Expired
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Abstract
To calibrate timing of test signals generated by all channels of an integrated circuit, each channel is programmed to generate a test signal having a repetitive pseudo-random test signal edge pattern. The test signal pattern of each channel is compared to a reference signal having the same edge pattern and the delay of each channel is adjusted to maximize cross-correlation between the test signal and the reference signal.
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