Lateral double diffused MOS transistor
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United States of America Patent
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Aug 19, 2003
Issued Date -
N/A
app pub date -
Feb 7, 2001
filing date -
Apr 26, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
To reduce ON-state resistance with desired withstand voltage secured, a semiconductor device provided with a gate electrode formed on a semiconductor substrate via a gate insulating film, an LP layer (a P-type body region) formed so that the LP layer is adjacent to the gate electrode, an N-type source region and a channel region respectively formed in the LP layer, an N-type drain region formed in a position apart from the LP layer and an LN layer (a drift region) formed so that the LN layer surrounds the drain region is characterized in that a P-type layer ranging to the LP layer is formed under the gate electrode.
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