Semiconductor package with singulation crease
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United States of America Patent
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Aug 26, 2003
Grant Date -
Apr 17, 2003
app pub date -
Oct 12, 2001
filing date -
Oct 12, 2001
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An integrated circuit chip package comprising a lead frame having an integrated circuit die electrically connected thereto. Partially encapsulating the lead frame and the integrated circuit die is a package body. The package body includes the central portion which is circumvented by a peripheral portion defining opposed top and bottom surfaces. Disposed in at least one of the top and bottom surfaces of the peripheral portion of the package body is a singulation crease. The singulation crease, which is formed in the package body during its molding process, is used to provide a stress concentration line which reduces stress along the edge of the chip package and avoids chipping and cracking problems during the punch singulation process used to complete the manufacture of the same.
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