Protective structure for bond wires

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6611053
APP PUB NO 20020031847A1
SERIAL NO

09841923

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Abstract

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A stereolithographic method for fabricating a protective structure for bond wires of a semiconductor device assembly. The stereolithographic method includes sequentially fabricating one or more layers of the protective structure. After a first layer is formed, each subsequent layer is superimposed upon, contiguous with, and mutually adhered to an underlying layer of the protective structure. The stereolithographic method is particularly useful for fabricating one or more protective structures for the bond wires of a test apparatus assembly that includes bond wires connecting the contact pads of a carrier substrate thereof to the corresponding bond pads of a test substrate of the test apparatus assembly. As it is desirable to assemble a semiconductor device to be tested with the test substrate, a fence member that receives such a semiconductor device and aligns the same with the test substrate can be assembled with the test substrate, over the one or more protective structures. The fence member can be formed integrally with the protective structures or it can be a preformed member that is secured over the protective structures. Stereolithographic processes can also be employed to fabricate the fence member. The stereolithographically fabricated structures, as well as semiconductor devices and assemblies including these structures, are also disclosed.

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Patent Owner(s)

Patent OwnerAddress
MICRON TECHNOLOGY INC8000 S FEDERAL WAY P O BOX 6 BOISE ID 83707-0006

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Akram, Salman Boise, ID 801 30978

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