Architecture for decimation algorithm
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United States of America Patent
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Aug 26, 2003
Grant Date -
N/A
app pub date -
Oct 9, 2001
filing date -
Oct 26, 2000
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A new architecture for implementing a digital algorithm such as a decimation algorithm is described. The new decimator circuit is well suited for digital circuits such as a delta-sigma (or sigma-delta) analog-to-digital converter. In particular, the new decimator circuit incorporates a general purpose architecture which enables a wide range of flexibility to change and modify the decimation algorithm performed by the decimator circuit. Moreover, the new decimator circuit can be fabricated in a smaller chip area than previously possible.
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