Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices
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United States of America Patent
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-
Sep 2, 2003
Grant Date -
Jul 4, 2002
app pub date -
Dec 28, 2000
filing date -
Dec 28, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
A multi-layer integrated circuit (400) and method of manufacturing thereof having barbed vias (427) connecting conductive lines (468, 408). Circuit (400) includes a first dielectric layer (404) deposited on a substrate (402) and conductive lines (408) formed in the first dielectric layer (404). A second dielectric layer (462) is deposited over the first dielectric layer (404). Barbed vias (427) are formed having a substantially cylindrical portion (424) within the second dielectric layer (462) and a barbed portion (426) within conductive lines (408). Conductive lines (468) are formed over the barbed vias (427) within a the second dielectric layer (462). A region of the barbed via (427) barbed portion (406) extends beneath the second dielectric layer (462).
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