Semiconductor non-volatile memory device having a NAND cell structure
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United States of America Patent
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Sep 2, 2003
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app pub date -
Jul 10, 2000
filing date -
Apr 16, 1998
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Abstract
A NAND stack array (95') is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors (10) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.
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