Selection based rounding system and method for floating point operations
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United States of America Patent
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-
Sep 2, 2003
Grant Date -
N/A
app pub date -
May 30, 2000
filing date -
May 30, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A selection based rounding system and method eliminate the need for post increment based rounding in a floating point (FP) fused multiply adder that can be utilized in a processor or other digital circuit to significantly increase speed. Generally, an unincremented result and an incremented result are produced in parallel and then either one is selected as a rounded result based upon specified rounding criteria, thereby eliminating the time consuming need for an incrementor to perform rounding at or near the end of the FP fused multiply adder.
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