VLIW processor accepting branching to any instruction in an instruction word set to be executed consecutively
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United States of America Patent
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-
Sep 2, 2003
Grant Date -
N/A
app pub date -
Jan 18, 2000
filing date -
Jul 19, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A VLIW processor includes an instruction decode unit selecting one of parallel execution and consecutive execution and decoding a plurality of operation instructions included in an instruction word, and a program counter control unit controlling a value of a program counter for providing an indication for the instruction decode unit to provide as no-operation an operation instruction provided in a consecutive execution and executed prior to an operation instruction executed during a consecutive execution when branching to the operation instruction executed during the consecutive execution is introduced. This renders it possible to branch to an operation instruction executed during a consecutive execution and thus provide an enhanced efficiency of instruction-code compression.
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