Importance

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Abstract

An isolated stack-gate flash cell structure comprises a gate region being formed between common-source/drain regions. The common-source/drain region comprises a pair of divided source/drain diffusion regions being isolated by an etched-back planarized field-oxide layer formed over a shallow trench in a semiconductor substrate and a pair of extended floating-gate spacers being formed over a portion of a pair of etched-back first sidewall dielectric spacers and the etched-back planarized field-oxide layer. The gate region comprises a major floating-gate being formed over a tunneling dielectric layer and integrated with nearby two extended floating-gate spacers to form an integrated floating-gate. A word line over an intergate dielectric layer is formed over the integrated floating-gate. The isolated stack-gate flash cell structure is used to form two contactless parallel divided source/drain diffusion bit-lines arrays.

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First Claim