Method, apparatus, and system for high speed data transfer using source synchronous data strobe
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United States of America Patent
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Sep 16, 2003
Grant Date -
N/A
app pub date -
Mar 31, 2000
filing date -
Jan 13, 2000
priority date (Note) -
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Abstract
According to one aspect of the invention, a method is provided in which a write strobe signal is generated to latch output data into a memory unit that comprises one or more dual data rate synchronous dynamic random access memory (DDR-SDRAM) devices. The write strobe signal has an edge transition at approximately the center of a data window corresponding to the output data. A first receive clock signal is delayed by a first delay period using a delay locked loop (DLL) circuit to generate a first delayed receive clock signal. The first delayed receive clock signal is used to latch incoming data from the memory unit.
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