Importance

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Abstract

A timing calibration system for a wafer level integrated circuit (IC) tester is disclosed. The tester includes channels linked by paths through an interconnect system to pads of the IC. During a test each channel may send a test signal edge to an IC pad following a clock signal edge with a delay including 'programmable drive' delay and 'drive calibration' delay components, or may sample an IC output signal following the clock signal edge with a delay including 'programmable compare' delay and adjustable 'compare calibration' delay components. The interconnect system also links a spare channel to a point on the IC. To adjust the compare calibration delay of each channel, the interconnect system sequentially connects the tester channels to interconnect areas on a 'calibration' wafer instead of to the IC on the wafer to be tested. Each interconnect area provides a path linking a channel to be calibrated to the spare channel. With the programmable drive delay of the channel being calibrated and the programmable compare and compare calibration delays of the spare channel set to standard values, the drive calibration delay of the channel being calibrated is adjusted so it sends a test signal edge to the spare channel close to when the spare channel samples it. Pairs of tester channels are then interconnected through another wafer interconnect area. Each channel then sends a test signal edge to the other tester channel with a standard delay following a clock signal edge to provide a reference for calibrating the receiving channel's compare calibration delay.

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First Claim