Content-addressable memory with cascaded match, read and write logic in a programmable logic device
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United States of America Patent
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Sep 16, 2003
Grant Date -
N/A
app pub date -
Sep 14, 2000
filing date -
Sep 14, 2000
priority date (Note) -
Expired
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Abstract
An apparatus comprising one or more memory blocks in a programmable logic device. The memory blocks may be configured as content-addressable memory having arbitrarily adjustable tag and data widths.
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