Methods for implementing circuits in programmable logic devices to minimize the effects of single event upsets
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United States of America Patent
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Sep 23, 2003
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N/A
app pub date -
May 16, 2002
filing date -
May 16, 2002
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Abstract
Methods for implementing a circuit in a programmable logic device (PLD) that protect the circuit from the effects of single event upsets. When routing nodes within the circuit using the interconnect lines of the PLD, two routed nodes are separated from each other by at least two programmable interconnect points (PIPs). Therefore, if a single event upset causes a PIP to become inadvertently enabled, the affected node is coupled to an unused interconnect line, instead of to another node within the circuit. In some embodiments, a triple modular redundancy (TMR) circuit is implemented. Signals in one module are separated from signals in another module by at least two PIPS. However, signals within the same module can be separated by only one PIP, because the TMR structure of the circuit can compensate for errors within a single module.
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