Memory based phase locked loop
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Sep 23, 2003
Grant Date -
N/A
app pub date -
Mar 30, 2000
filing date -
Mar 31, 1999
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A circuit comprising a phase detector/correction circuit, at least one column of memory cells, a control circuit and a sense amplifier. The control circuit may be configured to read a sequence from the memory cells in a predetermined order and present a first output signal. The sense amplifier may be configured to present a periodic signal in response to the first output signal.
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