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Abstract

A master-slave latch circuit for a multithreaded processor stores information for multiple threads. The basic cell contains multiple master elements, each corresponding to a respective thread, selection logic coupled to the master elements for selecting a single one of the master outputs, and a single slave element coupled to the selector logic. Preferably, the circuit supports operation in a scan mode for testing purposes. In scan mode, one or more elements which normally function as master elements, function as slave elements. When operating in scan mode using this arrangement, the number of master elements in the pair of cells equals the number of slave elements, even though the number of master elements exceeds the number of slave elements during normal operation, permitting data to be successively scanned through all elements of the circuit. In an alternative embodiment, elements function as in scan mode during a HOLD mode of operation, and a feedback loop controlled by a HOLD signal is added to each pair of master/slave elements. The feedback loop drives the master element with the value of the slave.

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First Claim