Importance

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Abstract

An elastic store circuit using a first in/first out buffer (FIFO) to accurately delay and manipulate a waveform using the write (WR) and read (RD) clocks is provided. The FIFO delays data by, first, reading the input data at the WR clock rate. Then, the data exits the FIFO in response to the RD clock. Large delays are accomplished by changing the relationship between the WR and RD clocks in whole clock intervals. Delays and adjustments of less than a whole clock interval are accomplished by changing the phase relationship of the RD clock with respect to the WR clock. The present invention generates the WR and RD clocks through synthesis using a lower frequency reference clock. The RD phase change results from introducing a phase change into the reference clock driving the RD clock synthesizer. A method of introducing precise delays through phase control of the WR and RD clocks is also provided.

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First Claim