Reduction of surface roughness during chemical mechanical planarization (CMP)
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United States of America Patent
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Oct 7, 2003
Grant Date -
Dec 5, 2002
app pub date -
Jul 30, 2002
filing date -
Feb 16, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
Improved methods, compositions and structures formed therefrom are provided that allow for reduction of roughness in layers (e.g., oxide layers) of a planarized wafer. In one such embodiment, improved methods, compositions and structures formed therefrom for reduction of roughness in layers (e.g., oxide layers) of a planarized wafer are used in conjunction with high modulus polyurethane pads. In one embodiment, improved methods, compositions and structures formed therefrom are provided that reduce rough interlayer dielectric (ILD) conditions for a wafer during CMP processing of such a wafer. Embodiments of a method for forming a microelectronic substrate include mixing a surfactant at least 100 parts per million (ppm) to slurries to form a polishing solution.
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