Method and apparatus for patching problematic instructions in a microprocessor using software interrupts
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United States of America Patent
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Oct 7, 2003
Grant Date -
N/A
app pub date -
Nov 8, 1999
filing date -
Nov 8, 1999
priority date (Note) -
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Abstract
A method and apparatus for patching a problematic instruction within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate a matched instruction. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. A matched instruction may be marked using a match bit that accompanies the instruction through the instruction pipeline. The matched instruction is then replaced with an internal opcode or internal instruction that causes the instruction scheduling unit to take a special software interrupt. The problematic instruction is then patched through the execution of a set of instructions that cause the desired logical operation of the problematic instruction.
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