Method for avoiding defects produced in the CMP process

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United States of America Patent

PATENT NO 6632742
APP PUB NO 20020155716A1
SERIAL NO

09836219

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Abstract

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A method for avoiding defects produced in The CMP process has the following steps: sequentially depositing a first dielectric layer and a second dielectric layer on a semiconductor substrate, wherein the wet-etching rate of the first dielectric layer is greater than the wet-etching rate of the second dielectric layer; forming a plurality of first holes on a plurality of the predetermined contact window areas respectively; wet etching the first dielectric layer in each of the first holes to form a plurality of second holes on the plurality of the predetermined contact window areas respectively; forming a conductive layer to fill each of the second holes; and performing the CMP process to level off the conductive layer and the second dielectric layer.

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Patent Owner(s)

Patent OwnerAddress
PROMOS TECHNOLOGIES INCA3 3F NO 1 LI HSIN 1ST RD HSINCHU SCIENCE PARK HSINCHU 30078

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Wang, Jiun-Fang Hsinchu, TW 25 559
Yang, Ming-Cheng Taipei, TW 13 382

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