Integrated circuit wiring with low RC time delay
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United States of America Patent
Stats
-
Oct 14, 2003
Grant Date -
Aug 23, 2001
app pub date -
Jun 3, 1999
filing date -
Jun 13, 1997
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The present invention is directed to a semiconductor interconnect structure comprised of a promoter layer defining openings and a metal layer having a portion elevated above the substrate assembly and a portion that fills the openings. The metal layer is in electrical contact with the substrate assembly through the portion of the metal layer that fills the openings. The portion of the metal layer that fills the openings supports the elevated portion of the metal layer. A method of fabricating a semiconductor interconnect structure is also provided. A resist layer is patterned on a substrate assembly to define openings. A metal layer is deposited on the resist layer and into the openings, and the resist layer is removed to form a gap between the metal layer and the underlying substrate assembly.
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